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Index: kernel/generic/src/console/kconsole.c
===================================================================
--- kernel/generic/src/console/kconsole.c	(revision 3467)
+++ kernel/generic/src/console/kconsole.c	(working copy)
@@ -51,6 +51,7 @@
 #include <func.h>
 #include <symtab.h>
 #include <macros.h>
+#include <test.h>
 
 /** Simple kernel console.
  *
@@ -410,6 +411,8 @@
 	cmd_info_t *cmd_info;
 	count_t len;
 	char *cmdline;
+	
+	test_thread1(false);
 
 	if (!stdin) {
 		printf("%s: no stdin\n", __func__);
Index: kernel/arch/sparc64/include/interrupt.h
===================================================================
--- kernel/arch/sparc64/include/interrupt.h	(revision 3467)
+++ kernel/arch/sparc64/include/interrupt.h	(working copy)
@@ -42,6 +42,9 @@
 #define IVT_ITEMS 	15
 #define IVT_FIRST	1
 
+// podle enumu uvedeneho pod timto definem se rozhoduje
+// jedna metoda v kernel/src/ipi.c, co delat. Kdyz by to bylo
+// nastaveno jinak, zpanikarila by
 /* This needs to be defined for inter-architecture API portability. */
 #define VECTOR_TLB_SHOOTDOWN_IPI	0
 
Index: kernel/arch/sparc64/include/trap/interrupt.h
===================================================================
--- kernel/arch/sparc64/include/trap/interrupt.h	(revision 3467)
+++ kernel/arch/sparc64/include/trap/interrupt.h	(working copy)
@@ -40,6 +40,8 @@
 #include <arch/trap/trap_table.h>
 #include <arch/stack.h>
 
+// tak nasledujici 4 definice se tykaji buhvi ceho... Pouzivaji se v ovladaci PCI a FHC, vic o tom nevim.
+
 /* IMAP register bits */
 #define IGN_MASK	0x7c0
 #define INO_MASK	0x1f
@@ -49,21 +51,43 @@
 
 
 /* Interrupt ASI registers. */
-#define ASI_UDB_INTR_W			0x77
+#define ASI_INTR_W			0x77
 #define ASI_INTR_DISPATCH_STATUS	0x48
-#define ASI_UDB_INTR_R			0x7f
+#define ASI_INTR_R			0x7f
 #define ASI_INTR_RECEIVE		0x49
 
 /* VA's used with ASI_UDB_INTR_W register. */
+#if defined (US)
 #define ASI_UDB_INTR_W_DATA_0	0x40
 #define ASI_UDB_INTR_W_DATA_1	0x50
 #define ASI_UDB_INTR_W_DATA_2	0x60
-#define ASI_UDB_INTR_W_DISPATCH	0x70
+#elif defined (US3)
+#define VA_INTR_W_DATA_0	0x40
+#define VA_INTR_W_DATA_1	0x48
+#define VA_INTR_W_DATA_2	0x50
+#define VA_INTR_W_DATA_3	0x58
+#define VA_INTR_W_DATA_4	0x60
+#define VA_INTR_W_DATA_5	0x68
+#define VA_INTR_W_DATA_6	0x80
+#define VA_INTR_W_DATA_7	0x88
+#endif
+#define VA_INTR_W_DISPATCH	0x70
 
 /* VA's used with ASI_UDB_INTR_R register. */
+#if defined(US)
 #define ASI_UDB_INTR_R_DATA_0	0x40
 #define ASI_UDB_INTR_R_DATA_1	0x50
 #define ASI_UDB_INTR_R_DATA_2	0x60
+#elif defined (US3)
+#define VA_INTR_R_DATA_0	0x40
+#define VA_INTR_R_DATA_1	0x48
+#define VA_INTR_R_DATA_2	0x50
+#define VA_INTR_R_DATA_3	0x58
+#define VA_INTR_R_DATA_4	0x60
+#define VA_INTR_R_DATA_5	0x68
+#define VA_INTR_R_DATA_6	0x80
+#define VA_INTR_R_DATA_7	0x88
+#endif
 
 /* Shifts in the Interrupt Vector Dispatch virtual address. */
 #define INTR_VEC_DISPATCH_MID_SHIFT	14
Index: kernel/arch/sparc64/include/trap/mmu.h
===================================================================
--- kernel/arch/sparc64/include/trap/mmu.h	(revision 3467)
+++ kernel/arch/sparc64/include/trap/mmu.h	(working copy)
@@ -76,6 +76,7 @@
 	PREEMPTIBLE_HANDLER fast_instruction_access_mmu_miss
 .endm
 
+// tl = "trap level" (v dobe pred vyvolanim tohoto trapu)
 .macro FAST_DATA_ACCESS_MMU_MISS_HANDLER tl
 	/*
 	 * First, try to refill TLB from TSB.
@@ -112,9 +113,9 @@
 	bz 0f						! page address is zero
 
 	sethi %hi(kernel_8k_tlb_data_template), %g2
-	ldx [%g2 + %lo(kernel_8k_tlb_data_template)], %g2
+	ldx [%g2 + %lo(kernel_8k_tlb_data_template)], %g2	! kernel_8k_tlb_data_template - nachazi se tam TTE data pro adresu zacatku fyzicke pameti
 	or %g3, %g2, %g2
-	stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG		! identity map the kernel page
+	stxa %g2, [%g0] ASI_DTLB_DATA_IN_REG		! identity map the kernel page - presneji receno fyz. := virt. + zacatek_fyz_pameti
 	retry
 
 	/*
@@ -125,6 +126,7 @@
 	 * the offending SAVE or RESTORE.
 	 */
 0:
+// moc te myslence nerozumim
 .if (\tl > 0)
 	wrpr %g0, 1, %tl
 .endif
Index: kernel/arch/sparc64/include/mm/frame.h
===================================================================
--- kernel/arch/sparc64/include/mm/frame.h	(revision 3467)
+++ kernel/arch/sparc64/include/mm/frame.h	(working copy)
@@ -59,8 +59,13 @@
 union frame_address {
 	uintptr_t address;
 	struct {
+#if defined (US)
 		unsigned : 23;
 		uint64_t pfn : 28;		/**< Physical Frame Number. */
+#elif defined (US3)
+		unsigned : 21;
+		uint64_t pfn : 30;		/**< Physical Frame Number. */
+#endif
 		unsigned offset : 13;		/**< Offset. */
 	} __attribute__ ((packed));
 };
Index: kernel/arch/sparc64/include/mm/tte.h
===================================================================
--- kernel/arch/sparc64/include/mm/tte.h	(revision 3467)
+++ kernel/arch/sparc64/include/mm/tte.h	(working copy)
@@ -50,7 +50,7 @@
 
 #include <arch/types.h>
 
-// TODO find out what this means
+/* TTE tag's VA_tag field contains bits <63:VA_TAG_PAGE_SHIFT> of the VA */
 #define VA_TAG_PAGE_SHIFT	22
 
 /** Translation Table Entry - Tag. */
Index: kernel/arch/sparc64/include/mm/mmu.h
===================================================================
--- kernel/arch/sparc64/include/mm/mmu.h	(revision 3467)
+++ kernel/arch/sparc64/include/mm/mmu.h	(working copy)
@@ -35,8 +35,10 @@
 #ifndef KERN_sparc64_MMU_H_
 #define KERN_sparc64_MMU_H_
 
+#if defined(US)
 /* LSU Control Register ASI. */
 #define ASI_LSU_CONTROL_REG		0x45	/**< Load/Store Unit Control Register. */
+#endif
 
 /* I-MMU ASIs. */
 #define ASI_IMMU			0x50
@@ -80,6 +82,7 @@
 #include <arch/barrier.h>
 #include <arch/types.h>
 
+#if defined(US)
 /** LSU Control Register. */
 typedef union {
 	uint64_t value;
@@ -100,6 +103,7 @@
 		
 	} __attribute__ ((packed));
 } lsu_cr_reg_t;
+#endif /* US */
 
 #endif /* !def __ASM__ */
 
Index: kernel/arch/sparc64/include/mm/as.h
===================================================================
--- kernel/arch/sparc64/include/mm/as.h	(revision 3467)
+++ kernel/arch/sparc64/include/mm/as.h	(working copy)
@@ -52,7 +52,8 @@
 typedef union tsb_tag_target {
 	uint64_t value;
 	struct {
-		unsigned invalid : 1;	/**< Invalidated by software. */
+		unsigned invalid : 1;	/**< Invalidated by software. */	// jeste se mrkni, kdo zde zapsanou hodnotu pouziva. Navic, manual tvrdi, ze posl. 3 bity tohoto registru maji byt 0, jak si muzeme dovolit nastavit je na neco jineho
+										// aha, v Jakubove diplomce se pise, ze je to trik, jak invalidovat zaznam v TSB - nastavime v prislusnem TSB entry jeden z poslednich tri bitu na 1 (TSB je zalezitost SW, nikoliv HW, takze si to muzem dovolit) a tak porovnani TSB tag target registru s tagem v TSB vzdy skonci s vysledkem "nemecuje"
 		unsigned : 2;
 		unsigned context : 13;	/**< Software ASID. */
 		unsigned : 6;
@@ -62,7 +63,7 @@
 
 /** TSB entry. */
 typedef struct tsb_entry {
-	tsb_tag_target_t tag;
+	tsb_tag_target_t tag;	// tady je trochu znasilnen bit G, misto nej je v prislusne ceckovske strukture bit "invalid"
 	tte_data_t data;
 } __attribute__ ((packed)) tsb_entry_t;
 
@@ -76,10 +77,13 @@
 typedef struct {
 } as_arch_t;
 
+// jasny, as_arch_t je struktura, do ktere si kazdy port muze ulozit nejake dodatecne informace o adresovem prostoru (takze treba takovy sparc64 si sem ulozi obsah TSB)
+
 #endif /* CONFIG_TSB */
 
 #include <genarch/mm/as_ht.h>
 
+// funkci as_invalidate_translation_cache bude volat genericky kod, funkce as_invalidate_translation_cache na sparcu nakonfigurovanem s podporou pro TSB invaliduje TSB
 #ifdef CONFIG_TSB
 #include <arch/mm/tsb.h>
 #define as_invalidate_translation_cache(as, page, cnt) \
Index: kernel/arch/sparc64/include/barrier.h
===================================================================
--- kernel/arch/sparc64/include/barrier.h	(revision 3467)
+++ kernel/arch/sparc64/include/barrier.h	(working copy)
@@ -82,6 +82,9 @@
 	asm volatile ("membar #Sync\n");
 }
 
+// jaky je presny ucel te write bariery? Jestlize, dle jj-thesis.pdf
+// funguje flush jako "full memory barrier", pak je tam
+// to write_barrier nadbytecne, ne?
 #define smc_coherence(a)	\
 {				\
 	write_barrier();	\
Index: kernel/arch/sparc64/src/cpu/cpu.c
===================================================================
--- kernel/arch/sparc64/src/cpu/cpu.c	(revision 3479)
+++ kernel/arch/sparc64/src/cpu/cpu.c	(working copy)
@@ -125,6 +125,15 @@
 	case IMPL_ULTRASPARCIII:
 		impl = "UltraSPARC III";
 		break;
+	case IMPL_ULTRASPARCIII_PLUS:
+		impl = "UltraSPARC III+";
+		break;
+	case IMPL_ULTRASPARCIII_I:
+		impl = "UltraSPARC IIIi";
+		break;
+	case IMPL_ULTRASPARCIV:
+		impl = "UltraSPARC IV";
+		break;
 	case IMPL_ULTRASPARCIV_PLUS:
 		impl = "UltraSPARC IV+";
 		break;
Index: kernel/arch/sparc64/src/start.S
===================================================================
--- kernel/arch/sparc64/src/start.S	(revision 3479)
+++ kernel/arch/sparc64/src/start.S	(working copy)
@@ -296,11 +296,11 @@
 	ba 0b
 	nop
 
-
 	/*
 	 * Read MID from the processor.
 	 */
 1:
+
 	ldxa [%g0] ASI_ICBUS_CONFIG, %g1
 	srlx %g1, ICBUS_CONFIG_MID_SHIFT, %g1
 	and %g1, ICBUS_CONFIG_MID_MASK, %g1
Index: kernel/arch/sparc64/src/smp/ipi.c
===================================================================
--- kernel/arch/sparc64/src/smp/ipi.c	(revision 3467)
+++ kernel/arch/sparc64/src/smp/ipi.c	(working copy)
@@ -46,6 +46,33 @@
 #include <time/delay.h>
 #include <panic.h>
 
+/** Set the contents of the outgoing interrupt vector data.
+ *
+ * The first data item (data 0) will be set to the value of func, the
+ * rest of the vector will contain zeros.
+ *
+ * This is a helper function used from within the cross_call function.
+ *
+ * @param func value the first data item of the vector will be set to
+ */
+static inline void set_intr_w_data(void (* func)(void))
+{
+#if defined (US)
+	asi_u64_write(ASI_INTR_W, ASI_UDB_INTR_W_DATA_0, (uintptr_t) func);
+	asi_u64_write(ASI_INTR_W, ASI_UDB_INTR_W_DATA_1, 0);
+	asi_u64_write(ASI_INTR_W, ASI_UDB_INTR_W_DATA_2, 0);
+#elif defined (US3)
+	asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_0, (uintptr_t)	func);
+	asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_1, 0);
+	asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_2, 0);
+	asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_3, 0);
+	asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_4, 0);
+	asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_5, 0);
+	asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_6, 0);
+	asi_u64_write(ASI_INTR_W, VA_INTR_W_DATA_7, 0);
+#endif
+}
+
 /** Invoke function on another processor.
  *
  * Currently, only functions without arguments are supported.
@@ -74,13 +101,10 @@
 		panic("Interrupt Dispatch Status busy bit set\n");
 	
 	do {
-		asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_0,
-		    (uintptr_t)	func);
-		asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_1, 0);
-		asi_u64_write(ASI_UDB_INTR_W, ASI_UDB_INTR_W_DATA_2, 0);
-		asi_u64_write(ASI_UDB_INTR_W,
+		set_intr_w_data(func);
+		asi_u64_write(ASI_INTR_W,
 		    (mid << INTR_VEC_DISPATCH_MID_SHIFT) |
-		    ASI_UDB_INTR_W_DISPATCH, 0);
+		    VA_INTR_W_DISPATCH, 0);
 	
 		membar();
 		
Index: kernel/arch/sparc64/src/sparc64.c
===================================================================
--- kernel/arch/sparc64/src/sparc64.c	(revision 3467)
+++ kernel/arch/sparc64/src/sparc64.c	(working copy)
@@ -37,6 +37,7 @@
 #include <config.h>
 #include <arch/trap/trap.h>
 #include <arch/console.h>
+#include <print.h>
 #include <proc/thread.h>
 #include <arch/drivers/simics_output.h>
 #include <console/console.h>
@@ -86,7 +87,7 @@
 		 * We have 2^11 different interrupt vectors.
 		 * But we only create 128 buckets.
 		 */
-		irq_init(1 << 11, 128);
+		irq_init(1 << 11, 128);	// zda se, ze konstanta 1 << 11 je definovana v dokumetaci k US2
 		
 		simics_output_init();
 		//standalone_sparc64_console_init();
@@ -110,7 +111,8 @@
 		/*
 	         * Create thread that polls keyboard.
 	         */
-		t = thread_create(kkbdpoll, NULL, TASK, 0, "kkbdpoll", true);
+		printf("task = %s", TASK->name);
+		t = thread_create(kkbdpoll, NULL, TASK, 0, "kkbdpoll", true); // TASK je soucasti THE struktury, v tuto chvili je TAKEm "kernel"
 		if (!t)
 			panic("cannot create kkbdpoll\n");
 		thread_ready(t);
@@ -126,7 +128,7 @@
  */
 void calibrate_delay_loop(void)
 {
-	CPU->delay_loop_const = 1;
+	CPU->delay_loop_const = 1;	// uz bylo zavolano cpu_init(), takze CPU na THE je
 }
 
 /** Wait several microseconds.
Index: kernel/arch/sparc64/src/trap/interrupt.c
===================================================================
--- kernel/arch/sparc64/src/trap/interrupt.c	(revision 3467)
+++ kernel/arch/sparc64/src/trap/interrupt.c	(working copy)
@@ -71,7 +71,11 @@
 	uint64_t data0;
 
 	intrcv = asi_u64_read(ASI_INTR_RECEIVE, 0);
-	data0 = asi_u64_read(ASI_UDB_INTR_R, ASI_UDB_INTR_R_DATA_0);
+#if defined (US)
+	data0 = asi_u64_read(ASI_INTR_R, ASI_UDB_INTR_R_DATA_0);
+#elif defined (US3)
+	data0 = asi_u64_read(ASI_INTR_R, VA_INTR_R_DATA_0);
+#endif
 
 	irq_t *irq = irq_dispatch_and_lock(data0);
 	if (irq) {
Index: kernel/arch/sparc64/src/mm/tsb.c
===================================================================
--- kernel/arch/sparc64/src/mm/tsb.c	(revision 3467)
+++ kernel/arch/sparc64/src/mm/tsb.c	(working copy)
@@ -66,10 +66,11 @@
 	if (pages == (count_t) -1 || (pages * 2) > ITSB_ENTRY_COUNT)
 		cnt = ITSB_ENTRY_COUNT;
 	else
-		cnt = pages * 2;
+		cnt = pages * 2;	// toto asi bude kvuli tomu, ze emulujeme 16kB stranky
 	
+	// tady se mi zda, ze se nektere stranky invaliduji zbytecne, ne? Konkretne se misto stranky x muze invalidovat i takova stranka y, ze x =/= y, ale cislo x a cislo y maji spolecnych nejmene vyznamnych 11 bitu
 	for (i = 0; i < cnt; i++) {
-		as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT - 1)].tag.invalid =
+		as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT - 1)].tag.invalid =	// to & (ITSB_ENTRY_COUNT - 1) bude asi moduleni poctem zaznamu v TSB
 		    true;
 		as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT - 1)].tag.invalid =
 		    true;
@@ -112,9 +113,9 @@
 	tsb->data.value = 0;
 	tsb->data.size = PAGESIZE_8K;
 	tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
-	tsb->data.cp = t->c;
-	tsb->data.p = t->k;		/* p as privileged */
-	tsb->data.v = t->p;
+	tsb->data.cp = t->c;	/* cp as cache in phys.-idxed, c as cacheable */
+	tsb->data.p = t->k;	/* p as privileged, k as kernel */
+	tsb->data.v = t->p;	/* v as valid, p as present */
 	
 	write_barrier();
 	
Index: uspace/app/init/init.c
===================================================================
--- uspace/app/init/init.c	(revision 3467)
+++ uspace/app/init/init.c	(working copy)
@@ -105,15 +105,14 @@
 	}
 	
 	// FIXME: spawn("/sbin/pci");
-	spawn("/sbin/fb");
+	//spawn("/sbin/fb");
 	spawn("/sbin/kbd");
 	spawn("/sbin/console");
 	
-	console_wait();
+	//console_wait();
 	version_print();
 	
 	spawn("/sbin/bdsh");
-	
 	return 0;
 }
 
Index: boot/arch/sparc64/loader/asm.S
===================================================================
--- boot/arch/sparc64/loader/asm.S	(revision 3479)
+++ boot/arch/sparc64/loader/asm.S	(working copy)
@@ -113,7 +113,6 @@
 	 * or not is decided according to the value of the ver.impl bits
 	 * in the Version register.
 	 */
-	sethi 0x40000, %g0
 ! the lowest/greatest value of ver.impl for US3
 #define FIRST_US3_CPU 0x14
 #define LAST_US3_CPU 0x19
@@ -144,6 +143,7 @@
 	mov %o1, %o0
 	mov %o2, %o1
 	mov %o3, %o2
+
 	jmp %l1				! jump to kernel
 	nop
 
Index: boot/arch/sparc64/loader/boot.S
===================================================================
--- boot/arch/sparc64/loader/boot.S	(revision 3467)
+++ boot/arch/sparc64/loader/boot.S	(working copy)
@@ -82,7 +82,7 @@
  
 	call ofw_init		! initialize OpenFirmware
 	stx %o4, [%l0]
-	
+
 	b bootstrap
 	nop